Silicon Designed to Be Verified
From RTL through to production silicon, with verification running alongside the design rather than after it.
IP/SoC Design Service
With 250+ years of collective engineering expertise, our team has delivered SoCs across AI, automotive, data center, consumer electronics, and memory controllers. We bring deep mastery of advanced architectures, memory subsystems, and high-speed interfaces to the most complex silicon challenges.
RTL Design
RTL delivered at block, IP, or SoC level. A fit for teams with a flow already in place who want one part of it taken on.
Full Front-End
RTL through synthesis and DFT as one engagement. Design and verification stay in one team, so there are fewer handover points.
Turnkey
Specification through to production, including foundry engagement and coordination with back-end partners.
We do not place engineers into a customer’s team as a staffing arrangement. The way we work rests on the environment we work in: checking against the model as the design goes, running regression in tiers, drawing on testbench assets we have already built. Send only the people and the method does not follow; what arrives is hours. So we prefer to do the work in our own environment. We can move quickly and accurately that way, and the difference shows in the schedule and in the quality of what you receive.
Hardware Comes With the Code That Drives It
An algorithm C model defines what a block should do. Our RTL designers work against that model as the reference: it produces expected results, and RTL simulation is checked against them from the first weeks of development through to sign-off. The C model stays an algorithm specification, and the algorithm owner keeps working on it.
Alongside the RTL, the same designers write the C code that actually drives the hardware: the register reads and writes, the initialization sequence, the ordering constraints that a register map alone never captures. Because that code grows with the RTL rather than being written afterwards from a document, it cannot fall out of step. When the design changes, the code changes with it, or the simulation stops passing.
What you receive is not only verified RTL. For an SoC, that driving code serves as a reference during chip test and silicon bring-up, when the question is whether the hardware or the software is at fault. For an IP block, it can be handed over as a working starting point for your device driver.
Two Ways to Hand Off a Design
Design Then Verify
- RTL delivered first, checked afterwards
- Bugs surface once the designer has moved on
- Register map handed over as a document
- Initialization order is something you ask the designer about
- Software team starts from scratch at bring-up
MetaEncore Approach
- RTL checked against the C model from early on
- Divergence found while the RTL can still be changed
- Driving C code that grows with the RTL
- Initialization and ordering arrive as working code, not a document
- A working reference in hand when silicon arrives
IP and Applications
IP
- ARM / RISC-V / MIPS
- PCIe Gen3 / Gen5
- NPU / GPU
- LPDDR5/4/4x, GDDR6
- USB 2.0/3.0
Application
- MCU
- Automotive Vision
- AI (On-Device, Edge, HPC)
- Surveillance Camera
- IoT / Sensor Control
The principle does not change for a new protocol or an unfamiliar domain: design it so it can be verified. Tell us which IP you are working with and we will propose where to start.
What You Receive
- RTL – Synthesizable code, documented with the design intent and structure behind it
- C Code – Register access, initialization, and ordering constraints in code that actually drives the hardware
- Reference Model – The algorithm model the RTL was checked against, handed over with it
- Verification Environment – The testbench and regression suite built alongside the design
- Synthesis & DFT – Constraint files, synthesis results, and scan insertion where the engagement covers front-end
- Knowledge Transfer – Handover documentation and walkthrough sessions so your team can pick it up
Have a Design Challenge?
Tell us about your architecture, your target application, and how far along the flow you need us to go, and we will work through the approach with you.